The present invention belongs to a technical field of a video processing for performing an encoding/decoding processing for video data by a processor which can be controlled by a program and the like, and relates to a video processing method and a video processing apparatus which include an address generating apparatus for generating an address for accessing a memory at transmitting data between more than two memories and which can perform an address control so as to access a video data of an effective video data region at accessing video data existing at outside the region of the effective video data stored in the memory.
In recent years, there is a growing concern about a system such as a visual telephone or a television conference, which system utilizes the video communication. However, since the transmission rate of the communication line employed in this system is generally low, a video encoding/encoding technique is necessary for transmitting a tremendous amount of video data and, actually, various kinds of encoding/decoding systems have so far been proposed. Further, under these circumstance, it is desired a video processing apparatus which performs video encoding/decoding processing by a processor controllable by a program and which can cope with various encoding/decoding systems flexibly by changing the program performing the control. Hereinafter, a conventional video processing apparatus which performs encoding/decoding processing by a processor controllable by a program will be described with reference to FIG. 13.
FIG. 13 is a block diagram illustrating a construction of a conventional video processing apparatus. This video processing apparatus includes, as shown in FIG. 13, a video input/output unit 1300 which inputs/outputs an input video or a display video, an external memory 1302 which memorizes video data or coded data, a processor unit 1303 which is operated by a program control, a DMA bus 1301 which performs the data transmission, in other words, the direct memory access (Direct Memory Access, hereinafter, referred to as xe2x80x9cDMAxe2x80x9d) between the video input/output unit 1300 or the processor unit 1303 and the external memory 1302, and a DMA control unit 1305 which controls the data transmission between the video input/output unit 1300 or the processor unit 1303 and the external memory 1302.
The processor unit 1303 comprises an encoding/decoding unit 1304 which encodes/decodes video data stored in the external memory 1302.
The DMA control unit 1302 comprises a DMA setting holding unit 1306 which stores the setting information required for generating an access address to the external memory 1302, a two dimensional address generating unit 1307 which generates an access address of the external memory 1302 in accordance with the setting information of the DMA setting holding unit 1306, and a DRAM control unit 1308 which controls reading or writing from/to the access address of the external memory 1302, which access address is generated from the two dimensional address generating unit 1307.
The video processing apparatus thus constructed, will be described in brief with reference to FIG. 13 and FIG. 14 particularly on the operation thereof.
At first, when an input video is input to the video input/output unit 1300, the input video is subjected to the resolution conversion into the video size as a target of encoding ,and thereafter, transmitted to the external memory 1302 through the DMA bus 1301 by the control of the DMA control unit 1305. As the encoding object video size after performing the resolution conversion, for example, QCIF, which is constituted by horizontal 176 pixelsxc3x97vertical 144 pixels, or CIF, which is constituted by horizontal 352 pixelsxc3x97vertical 288 pixels or the like are employed. The processor unit 1303 divides the encoding object video into rectangular regions of horizontal 16 pixelsxc3x97vertical 16 pixels or horizontal 8 pixelsxc3x97vertical 8 pixels, to take in the result into the encoding/decoding unit 1304, and thereafter, performs the encoding processing, and stores the coded data in the external memory 1302. When performing DMA for the encoding object video from the external memory 1302 to the encoding/decoding unit 1304 in the processor unit 1303, when the processor 1303 sets the setting information for generating a rectangular access address to the DMA setting holding unit 1306, the two dimensional address generating unit 1307 generates an address of the external memory 1302 in which data of the rectangular region are stored by employing the setting information. The two dimensional address generating unit 1307 for generating the rectangular access address can be realized by a construction disclosed in Japanese Published Patent Application No. Hei.4-218847. That is, the two dimensional address generating device 1307 is constituted to have an accumulation register for writing the address value that is employed actually as well as a first to N-th accumulation registers which are independent in each scan direction and, it is constructed such that, when the scan direction is switched, the address value is calculated by that the incremental data of the scan direction is added to the accumulation register corresponding to the scan direction. Thereby, since N pieces of accumulation registers hold the results of the address calculation that is previously performed for that scan direction until the scan direction becomes the same scan direction next time, there is no need to calculate an start address and set the result to the accumulation register every time when the scan direction is switched, and therefore, it is possible to access multi-dimensional data of a part of multi-dimensional region among the multi-dimensional address region, successively.
Further, as for the decoding processing, coded data, stored in the external memory 1302, which were transmitted from another video processing apparatus are direct memory accessed to the encoding/decoding unit 1304 in the processor unit 1303, to be decoded in units of the rectangular region, and the decoded video data are stored in the external memory 1302.
FIG. 14 is a diagram illustrating the video data stored in the external memory 1302. In FIG. 14, 1400 denotes pixel data DMA performed from the video input/output unit 1300 to the external memory 1302. The numbers in the circles represent pixel positions, in more detail, the upper numbers represent pixel positions in the horizontal direction and the lower numbers represent pixel positions in the vertical direction. 1401 denotes an effective video data region DMA performed from the video input/output unit 1300 to the external memory 1302 and, in this case, shows horizontal 176 pixels and vertical 144 pixels. 1402 denotes a first pixel data extended region which is obtained by copying a pixel data (0, 0) at the top-left corner of the effective video data region 1401, 1403 denotes a second pixel data extended region which is obtained by copying a pixel data (0, 175) at the top-right corner of the effective video data region 1401, 1404 denotes a third pixel data extended region which is obtained by copying a pixel data (143, 175) at the bottom-right corner of the effective video data region 1401, 1405 denotes a fourth pixel data extended region which is obtained by copying a pixel data (143, 0) at the bottom-left hand corner of the effective video data region 1401, 1406 denotes a fifth pixel data extended region which is obtained by copying a pixel data line at the top of the effective video data region 1401, 1407 denotes a sixth pixel data extended region which is obtained by copying a pixel data line at the right corner of the effective video data region 1401, 1408 denotes a seventh pixel data extended region which copies a pixel data line at the bottom of the effective video data region 1401, and 1409 denotes an eighth pixel data extended region which copies a pixel data line at the left corner of the effective video data region 1401.
On the other hand, as an international standard of the encoding system for a television conference system, there is ITU-T recommendation H.263 standard. This H.263 standard is provided with option modes in order to enhance the encoding efficiency, among which there is a non-limited moving vector mode. This mode is disclosed in xe2x80x9cTTC standard JT-H263 low-bit-rate communication video coding methodxe2x80x9d published by Corporate Juridical Person: Telegraph and Telephone Technology Committee. Briefly explained, it provides a moving compensation function using a moving vector showing an object which has jumped out of the effective video data region, and it is recognized it can enhance the encoding efficiency for a video which has low resolution and a video which is imaged by a moving camera.
Next, a description is given of a process of producing the extended regions 1402xcx9c1409 existing outside the effective video data region 1401 in the conventional video processing apparatus. When performing DMA from the video input/output unit 1300 in FIG. 13 to the external memory 1302, the effective data region 1401 in FIG. 14 is stored in the external memory 1302. Then, the processor 1303 in FIG. 13 copies pixel data existing at the corner of the effective data region 1401 stored in the external memory 1302 to the extended regions 1402xcx9c1409. Thus, an encoding processing using the non-limited moving vector mode is carried out. In this way, the extended regions 1402xcx9c1409 existing at outside the effective video data region 1401 are produced.
However, in the conventional video processing apparatus thus constituted, since the extended regions 1402xcx9c1409 are previously produced by the processor unit 1303 inside the external memory 1302 before starting the encoding processing of the non-limited moving vector mode, a memory capacity for the extended regions 1402xcx9c1409 is required, thereby resulting in an increase in the capacity of the external memory 1302.
In addition, since the processor unit 1303 produces the extended regions 1402xcx9c1409, a processing load of the processor unit 1303 would increase, thereby increasing the time required for the encoding process.
The present invention is made in view of the above-described problems, and has for its object to provide a method and an apparatus for video processing which prevents an in crease in the required capacity of the external memory at the data transmission between the external memory and the processor unit and further, can reduce the processing load of the processor unit.
According to a first aspect of the present invention, there is provided a video processing method, which comprises a processor unit for performing an encoding/decoding processing to data stored in a memory setting the setting information to a setting information holding unit, an address generating unit generating a rectangular access address according to the setting information, a memory control unit controlling the writing of the reading to/from the memory in accordance with the rectangular access address to perform the data transmission, which further comprises controlling, apart from the address generating unit, access positions in the horizontal direction and in the vertical direction and, when an access position exists at outside an effective data region, controlling an address of the address generation unit so as have an address value indicating the effective data region, thereby to perform a processing of video data compensation.
According to the present invention, it is only necessary for the memory to hold the effective video data, and therefore, it is possible to prevent an increase in the memory capacity required and, further reduce the processing load of the processor unit.
According to a second aspect of the present invention, there is provided a video processing apparatus for encoding or decoding effective video data stored in a memory, which makes the memory store only the effective video data therein, and when an encoding/decoding unit encodes or decodes a pixel data existing outside the effective video data region, encodes or decodes data existing at the periphery of the effective data region stored in the memory, which periphery is closest to the pixel data, by the address control or the address conversion.
According to the present invention, it is only necessary for memory to hold the effective video data, and therefore, it is possible to prevent an increase in the memory capacity required. Further there is no need to carry out an extension of the effective data region to an extended region previously, thereby it is possible to reduce a load for the extension processing.
According to a third aspect of the present invention, there is provided a video processing apparatus which includes a video input/output unit which makes video data input/output, a memory which stores video data and coded data, a processor unit which comprises an encoding/decoding unit for outputting setting information required for generating a rectangular access address of a rectangular region to be accessed to the memory and performing an encoding/decoding processing to the data stored in the memory, an address generating unit which generates the rectangular access address and further, generates a horizontal conclusion signal when the address generation in the horizontal direction is concluded and a vertical conclusion signal when the address generation in the vertical direction is concluded, while generating the rectangular access address, a setting information holding unit which holds setting information issued from the processor unit, which setting information is required for generating the rectangular access address by the address generating unit, an address control unit which administrates a horizontal or vertical access position to the memory on the basis of the setting information, the horizontal conclusion signal, and the vertical conclusion signal, detects whether or not the access position is within a region stored in the memory, and outputs an operation authorizing signal to the address generating unit when it is within the region, while does not output the operation authorizing signal to the address generation unit when it is not within the region, thereby to control the address generation by the address generation unit, and a memory control unit which controls the writing or the reading to/from the memory according to the rectangular access address generated from the address generating unit.
According to the present invention, it is possible to control an access address to outside the effective video data region so as to be an address of a video data at the edge of the effective video data region, thereby it is possible to prevent an increase in the required capacity of the external memory at the data transmission between an external memory and a processor unit, and further, to reduce the processing load of the processor unit.
According to a fourth aspect of the present invention, there is provided a video processing apparatus which includes a video input/output unit which makes video data input/output, a memory which stores video data and coded data, a processor unit which comprises an encoding/decoding unit for outputting setting information required for generating a rectangular access address of an access rectangular region to be accessed to the memory and performing an encoding/decoding processing to the data stored in the memory, an address generating unit which generates the rectangular access address and further, generates a horizontal conclusion signal when the address generation in the horizontal direction is concluded and a vertical conclusion signal when the address generation in the vertical direction is concluded, when generating the rectangular access address, a setting holding unit which holds the horizontal start position information, the horizontal position displacement information, the horizontal position limit value information, the vertical start position information, the vertical position displacement information, and the vertical position limit value information as the setting information issued from the processing unit, which setting information are required for generating the rectangular access address by the address generating unit, an address control unit which comprises a horizontal position control unit for controlling an access position in the horizontal direction, according to the horizontal start position information and the horizontal position displacement information, and a vertical position control unit for controlling an access position in the vertical direction, according to the vertical start position information and the vertical position displacement information, and further comprises an operation authorizing signal generating unit which generates an operation authorizing signal for authorizing the operation of the address generating unit according to the horizontal positional information issued from the horizontal position control unit, the vertical position information issued from the vertical position control unit, the horizontal position limit value information and the vertical position limit value information issued from the setting information holding unit respectively, and the horizontal conclusion signal and the vertical conclusion signal issued from the address generating unit respectively, and a memory control unit which controls the writing or the reading to/from the memory according to the rectangular access address generated from the address generating unit.
According to the present invention, it is possible to control an access address to outside the effective video data region so as to be an address of a video data at the periphery of the effective video data region, thereby it is possible to prevent an increase in the required capacity of the external memory at the data transmission between an external memory and a processor unit, and further to reduce the processing load of the processor unit.
According to a fifth aspect of the present invention, there is provided a video processing apparatus which includes a video input/output unit which makes video data input/output, an external memory which stores video data and coded data, and an encoding/decoding unit which decides an access rectangular region to be read out from the external memory, and reads out data of the effective access rectangular region included in the effective video data region among the access rectangular region from the external memory, thereby to perform the encoding/decoding processing thereto, wherein the encoding/decoding unit comprises a data processing unit for performing the encoding/decoding processing to data, an internal memory for storing the data of the effective access rectangular region read out from the external memory, a control unit for producing a data processing rectangular region which is to be transmitted from the internal memory to the data processing unit in the access rectangular region and outputting a start address of the data processing rectangular region and an extension pattern indicating a relative position between the access rectangular region and the effective video data region, an address generating unit for generating an access address in the data processing rectangular region with the start address as a start position, and an address conversion unit which outputs the address to the internal memory as it is when an address generated from the address generating unit is within the effective access rectangular region, and converts the address generated from the address generating unit into an address within the effective access rectangular region, on the basis of the extension pattern when an address generated from the address generating unit is not within the effective access rectangular region, and outputs the result to the internal memory.
According to the present invention, since it is not necessary for the internal memory and the external memory to store data of the extended region, it is possible to prevent an increase in the memory capacity required. Further, since it is not necessary to perform an extension of an effective video data region to the extended region previously, it is possible to reduce the load for the extension processing.
According to a sixth aspect of the present invention, in a video processing apparatus of the fifth aspect, the address conversion unit holds a table for the address conversion and performs the address conversion by employing the table.
According to the present invention, since it is not necessary for the internal memory and the external memory store data of the extended region, it is possible to prevent an increase in the memory capacity required. Further, since there is no need to perform an extension of an effective video data region to the extended region previously, it is possible to reduce the load for the extension processing. Furthermore, when realizing the address conversion by hardware, it is possible to reduce the processing load due to software in the encoding/decoding unit. Further, since such as multiplying processing are not required in the address conversion employing a table, it is not necessary to provide such as multipliers in the hardware, thereby resulting in reduction in the hardware size.